The present invention relates to a frequency-dividing circuit in a semiconductor integrated circuit or the like.
A prior art of the field concerned is shown in Denshi Joho Tsushin Gakkai Soritsu 70-Shunen Kinen Sogo Zenkoku Taikai Koen Ronbunshu (Papers from the 70th Anniversary Memorial Meeting of the Institute of Electronics, Information and Communication Engineers of Japan), No. 396 (Sho 62), Osafune, Enoki, Muraguchi and Owada "20GHzGaAs Dynamic Frequency-Divider", pages 2-200. This prior art will be explained with reference to the drawings.
FIG. 1 is a block diagram showing an example of a prior art frequency-dividing circuit.
In this frequency-dividing circuit, an inverter 1, a switch 2, a source-follower circuit 3, and a switch 4 are connected in a ring. The inputs of the respective inverters 1 and 3 are connected through capacitors 5 and 6 to the ground. An output terminal OUT is connected to the output of the source-follower circuit 3.
FIG. 2 is a circuit diagram of the frequency-dividing circuit in FIG. 1.
In this frequency-dividing circuit, the inverter 1 is comprised of a field-effect transistor (hereinafter referred to as FET) 1a, 1b, 1c and 1d and Schottky diode 1e and 1f. The switches 2 and 4 are comprised of FETs 2a and 4a, respectively, and the source-follower circuit 3 is comprised of FETs 3a and 3b. The capacitor 5 in FIG. 1 is a representation by a concentrated constant of the input capacitance of the gate of the FET 1b and the capacitance of the wiring conductor connected to the gate. Similarly, the capacitor 6 is a representation by a concentrated constant of the input capacitance of the gate of the FET 3a and the capacitance of the wiring conductor connected to the gate.
Vdd and Vss in FIG. 2 are a first and second power supply potentials, CK is a clock signal, CK is an inverted clock signal, and N1, N2 and N3 are nodes.
The operation of the frequency-dividing circuit will first be described with reference to FIG. 1.
It is assumed that, initially, the capacitance 5 is charged, the switch 2 is closed and the switch 4 is open. In this state, a High signal (an "H" level signal) is fed to the input of the inverter 1, and a Low signal (an "L" level signal) is delivered from the output of the inverter 1. Since the switch 2 is closed, the capacitance 6 is discharged and a Low signal is fed to the input of the source-follower circuit 3, and the output of the source-follower circuit 3 is Low.
When the switch 2 is opened, and the switch 4 is closed, since the output of the source-follower circuit 3 is Low, the capacitance 5 is discharged and the input of the inverter 1 becomes Low, and hence the output of the inverter 1 becomes High.
When the switch 2 is closed and the switch 4 is opened, the capacitance 6 is charged by the output of the inverter 1, and a High signal appears at the input of the source-follower circuit 3 and a High signal appears at the output of the source-follower circuit 3.
Accordingly, a signal having a period twice that of the opening and closing period of the switches 2 and 4 is fed to the output terminal OUT connected to the output of the source-follower circuit 3. Thus, the circuit operates as a frequency-dividing circuit.
When the capacitance 5 is charged with the switch 4 open, the charge on the capacitance 5 is discharged by a leak current through the input impedance of the inverter 1 and the switch 4, so it is impossible for this state to continue for a more than a certain time. Similarly, the charge on the capacitance 6 while the switch 2 is open cannot last long because of a leak current through the input impedance of the source-follower circuit 3 and the switch 2. The frequency-dividing circuit therefore operates as a dynamic frequency-dividing circuit which performs the frequency-dividing operation on signals of a period within a certain range which is limited by the charging and discharging time of the capacitances 5 and 6, and the delay time from the input to the output of the inverter 1 and the source-follower circuit 4.
Next, the operation of the frequency-dividing circuit in FIG. 1 will be described in further detail with reference to the timing chart of FIG. 3.
It is assumed that initially the clock signal CK, the nodes N2 and N3 and the output terminal OUT are Low, while the inverted clock signal CK and the node N2 are High. When the clock signal CK changes from Low to High, and the inverted clock signal CK changes from High to Low, the signal on the node Nl is transferred through FET 2a to the node N2, and the node N2 therefore changes from Low to High. The output terminal OUT therefore changes from Low to High. When the clock signal CK changes from High to Low, and the inverted clock signal CK changes from Low to High, the signal on the output terminal OUT is transferred through the FET 4a to the node N3, and the node N3 therefore changes from Low to High. The node N1 therefore changes from High to Low. In this way, a signal having a period twice that of the clock signal CK and the inverted clock signal CK appears at the output terminal OUT. The circuit thus operates as a frequency-dividing circuit.
The frequency-dividing circuit of the structure described above has the following problems.
In the frequency-dividing circuit in FIG. 2, if there is a delay between the phases of the clock signal CK and the inverted clock signal CK, and the interval for which they are both Low or both High is long, in which interval the levels on the various nodes are indefinite, and the circuit fails to operates successfully as a frequency-dividing circuit. That is, this circuit requires two-phase clock signals to be input, and their phases to be adjusted optimally.